IDT7034S_15 Datasheet, PDF (14/19 Pages) Integrated Device Technology – HIGH-SPEED 4K x 18 DUAL-PORT STATIC RAM

IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Waveform of Interrupt Timing⁽¹⁾
tWC
ADDR"A"
tAS ⁽³⁾
INTERRUPT SET ADDRESS ⁽²⁾
CE"A"
Industrial and Commercial Temperature Ranges
tWR ⁽⁴⁾
R/W"A"
INT"B"
ADDR"B"
CE"B"
tINS ⁽³⁾
tAS ⁽³⁾
tRC
INTERRUPT CLEAR ADDRESS ⁽²⁾
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OE"B"
INT"B"
tINR ⁽³⁾
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
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Truth Table III — Interrupt Flag⁽¹⁾
Left Port
R/WL
CEL
OEL
A0L-A11L
INTL
R/WR
L
L
X
FFF
X
X
X
X
X
X
X
X
X
X
X
X
L⁽³⁾
L
X
L
L
FFE
H⁽²⁾
X
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
Right Port
CER
OER
A0R-A11R
X
X
X
L
L
FFF
L
X
FFE
X
X
X
INTR
Function
L⁽²⁾ Set Right INTR Flag
H⁽³⁾ Reset Right INTR Flag
X Set Left INTL Flag
X Reset Left INTL Flag
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