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IDT7034S_15 Datasheet, PDF (1/19 Pages) Integrated Device Technology – HIGH-SPEED 4K x 18 DUAL-PORT STATIC RAM
HIGH-SPEED
4K x 18 DUAL-PORT
STATIC RAM
IDT7034S/L
Features:
◆ True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆ High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
◆ Low-power operation
– IDT7034S
Active: 850mW (typ.)
Standby: 5mW (typ.)
– IDT7034L
Active: 850mW (typ.)
Standby: 1mW (typ.)
◆ Separate upper-byte and lower-byte control for multi-
plexed bus compatibility
◆ IDT7034 easily expands data bus width to 36 bits or more
Functional Block Diagram
R/WL
UBL
using the Master/Slave select when cascading more than
one device
◆ M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
◆ Interrupt Flag
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ Battery backup operation—2V data retention
◆ TTL-compatible, single 5V (±10%) power supply
◆ Available in 100-pin Thin Quad Flatpack
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆ Green parts available. See ordering information
R/WR
UBR
LBL
CEL
OEL
I/O9L-I/O17L
I/O0L-I/O8L
BUSYL(1,2)
I/O
Control
I/O
Control
A11L
A0L
Address
Decoder
13
CEL
OEL
R/WL
MEMORY
ARRAY
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL(2)
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
Address
Decoder
CER
OER
R/WR
1
©2015 Integrated Device Technology, Inc.
LBR
CER
OER
I/O9R-I/O17R
.
I/O0R-I/O8R
BUSYR(1,2)
A11R
A0R
SEMR
INTR(2)
4089 drw 01
JUNE 2015
DSC 4089/10