IDT7034S_15 Datasheet, PDF (11/19 Pages) Integrated Device Technology – HIGH-SPEED 4K x 18 DUAL-PORT STATIC RAM

IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range⁽⁶⁾
7034X15
Com'l Only
Symbol
Parameter
Min.
Max.
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
15
tBDA
BUSY Disable Time from Address Not Matched
____
15
tBAC
BUSY Acce ss Time from Chip Enable Low
____
15
tBDC
BUSY Acce ss Time from Chip Enable High
____
15
7034X20
Com'l & Ind
Min.
Max. Unit
____
20
ns
____
20
ns
____
20
ns
____
17
ns
tAPS
Arbitration Priority Set-up Time⁽²⁾
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data⁽³⁾
____
18
____
30
ns
tWH
Write Hold After BUSY⁽⁵⁾
BUSY TIMING (M/S=VIL)
12
____
15
____
ns
tWB
BUSY Input to Write⁽⁴⁾
0
____
0
____
ns
tWH
Write Hold After BUSY⁽⁵⁾
12
____
15
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay⁽¹⁾
____
30
____
45
ns
tDDD
Write Data Valid to Read Data Delay⁽¹⁾
____
25
____
30
ns
NOTES:
4089 tbl 14
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH)" or "Timing Waveform of Write With
Port-To-Port Delay (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention with Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention with Port "A".
6. 'X' in part numbers indicates power rating (S or L).
61.412