ICS9LRS4103 Datasheet, PDF (13/15 Pages) Integrated Device Technology – 32-pin CK505 for Intel Systems

ICS9LRS4103
PC MAIN CLOCK
Byte 9 Amplitude Control Register
Bit Pin
Name
Description
7
Reserved
Reserved
6
Reserved
Reserved
5
REF Strength
Sets the REF output drive strength
4
Reserved
Reserved
3
Reserved
Reserved
2
IO_VOUT2
IO Output Voltage Select (Most Significant Bit)
1
IO_VOUT1
IO Output Voltage Select
0
IO_VOUT0
IO Output Voltage Select (Least Significant Bit)
Byte 10 Reserved Register
Bit Pin
Name
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 11 iAMT Enable Register
Bit Pin
Name
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
CPU0_AMT_EN
1
PCI-E_GEN2
0
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
M1 mode clk enable
Determines if PCI-E Gen2 compliant
Reserved
Byte 12 Byte Count Register
Bit Pin
Name
7
Reserved
6
Reserved
5
BC5
4
BC4
3
BC3
2
BC2
1
BC1
0
BC0
Description
Read Back byte count register,
max bytes = 32
Type
RW
R
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
R
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
1X (2Loads)
-
-
1
-
-
2X (3 Loads)
-
-
See Table 2: V_IO Selection
(Default is 0.8V)
Default
0
0
1
0
0
1
0
1
0
1
Default
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
1
-
-
1
0
-
Disable
non-Gen2
-
1
-
Enable
PCI-E Gen2
Compliant
-
Default
0
0
0
1
0
1
1
1
0
1
Default
0
0
0
0
1
1
0
1
IDT^® PC MAIN CLOCK
13
1520A—03/16/10