ICS9LRS4103 Datasheet, PDF (11/15 Pages) Integrated Device Technology – 32-pin CK505 for Intel Systems

ICS9LRS4103
PC MAIN CLOCK
Byte 0 FS Readback and PLL Selection Register
Bit Pin
Name
Description
Type
0
7
FSLC
CPU Freq. Sel. Bit
R
6
Reserved
Reserved
RW
-
5
Reserved
Reserved
RW
-
4
iAMT_EN
Set via SMBus
RW
(Sticky 1)
Legacy Mode
3
Reserved
Reserved
RW
2
SEL_120M#
Selects pins #10/11 to be 120MHz or 100MHz
R
120MHz
1
SEL_SATA_NS#
Select source for SATA clock
R
SATA
(100MHz_nonSS)
1 = on Power Down de-assert return to last known
state
0 = clear all SMBus configurations as if cold power-
Configuration Not
0
PD_Restore
on and go to latches open state
RW
Saved
This bit is ignored and treated at '1' if device is in
iAMT mode.
1
-
-
iAMT Enabled
100MHz
SRC1
(100MHz SS)
Configuration
Saved
Default
Latch
0
1
0
0
Latch
Latch
1
Byte 1 CPU/SRC Spread Selection Register
Bit Pin
Name
Description
7
Reserved
Reserved
6
CK505 PLL1_SSC_SEL
Select 0.5% down or center SSC
5
Reserved
Reserved
4
Reserved
Reserved
3
Reserved
Reserved
2
Reserved
Reserved
1
Reserved
Reserved
0
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
Down spread
-
-
-
-
-
-
1
-
Center spread
-
-
-
-
-
-
Default
0
0
0
0
0
0
1
1
Byte 2 Output Enable Register
Bit Pin
Name
7
REF_3L_OE
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Description
Output enable for REF0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
-
-
-
-
-
-
-
1
Output Enabled
-
-
-
-
-
-
-
Default
1
1
1
1
1
1
1
1
Byte 3 Reserved Register
Bit Pin
Name
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
RW
-
1
Default
-
1
-
1
-
1
-
1
-
1
-
1
1
-
1
IDT^® PC MAIN CLOCK
11
1520A—03/16/10