89HPES64H16G2 Datasheet, PDF (13/57 Pages) Integrated Device Technology – Low latency cut-through architecture

IDT 89HPES64H16G2 Data Sheet
Signal
PERSTN
RSTHALT
SWMODE[3:0]
Type
Name/Description
I Global Reset. Assertion of this signal resets all logic inside PES64H16G2.
I Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES64H16G2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
I Switch Mode. These configuration pins determine the PES64H16G2
switch operating mode. Note: These pins should be static and not change
following the negation of PERSTN.
0x0 - Single partition
0x1 - Single partition with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Single partition with port 0 selected as the upstream port (port 2 dis-
abled)
0x9 - Single partition with port 2 selected as the upstream port (port 0 dis-
abled)
0xA - Single partition with Serial EEPROM initialization and port 0 selected
as the upstream port (port 2 disabled)
0xB - Single partition with Serial EEPROM initialization and port 2 selected
as the upstream port (port 0 disabled)
0xC - Multi-partition
0xD - Multi-partition with Serial EEPROM initialization
0xE - Reserved
0xF - Reserved
Table 6 System Pins (Part 2 of 2)
13 of 57
November 28, 2011