83PR226I-01 Datasheet, PDF (13/22 Pages) Integrated Device Technology – Programmable FemtoClock LVPECL Oscillator Replacement

83PR226I-01 Datasheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended
only as guidelines.
The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible signals. Therefore, terminating
resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component
process variations.
Figure 4A. 3.3V LVPECL Output Termination
3.3V
3.3V
R3
R4
125
125
3.3V
Z_o = 50
+
Z_o = 50
R1
84
_
R2
84
Input
Figure 4B. 3.3V LVPECL Output Termination
©2017 Integrated Device Technology, Inc.
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April 13, 2017