ICS85411I Datasheet, PDF (11/16 Pages) Integrated Device Technology – LOW SKEW, 1-TO-2 DIFFERENTIAL-TOLVDS FANOUT BUFFER

ICS85411I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85411I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85411I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 10% = 3.63V, which gives worst case results.
DD
• Power (core) = V * I = 3.63V * 50mA = 181.5mW
MAX
DD_MAX
DD_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows:
Tj
=
θ_JA
*
Pd_total
+
T
A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T = Ambient Temperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming a
JA
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.182W * 103.3°C/W = 103.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE θ FOR 8-LEAD SOIC, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
153.3°C/W
112.7°C/W
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT^™ / ICS^™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER
11
ICS85411AMI REV. B NOVEMBER 7, 2007