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| ICS8534-01 Datasheet, PDF (11/20 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER | |||
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ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 4A to 4F show interface
examples for the HiPerClockS PCLK/nPCLK input driven by the
most common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
3.3V
CML
Zo = 50â¦
Zo = 50â¦
3.3V
R1
R2
50
50
3.3V
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
3.3V
CML Built-In Pullup
Zo = 50â¦
Zo = 50â¦
3.3V
PCLK
R1
100
nPCLK
HiPerClockS
PCLK/nPCLK
Figure 4A. HiPerClockS PCLK/nPCLK Input
Driven by an Open Collector CML Driver
3.3V
LVPECL
Zo = 50â¦
Zo = 50â¦
3.3V
R3
R4
125
125
3.3V
PCLK
nPCLK
HiPerClockS
R1
R2
84
84
Input
Figure 4B. HiPerClockS PCLK/nPCLK Input
Driven by a Built-In Pullup CML Driver
3.3V
3.3V LVPECL
Zo = 50â¦
Zo = 50â¦
R5
100 - 200
R6
100 - 200
3.3V
R3
R4
84
84
C1
C2
R1
R2
125 125
3.3V
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
Figure 4C. HiPerClockS PCLK/nPCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
SSTL
Zo = 60â¦
Zo = 60â¦
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
HiPerClockS
PCLK/nPCLK
Figure 4D. HiPerClockS PCLK/nPCLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
3.3V
Zo = 50â¦
LVDS
R5
100
Zo = 50â¦
3.3V
3.3V
R3
R4
1k
1k
C1
PCLK
C2
nPCLK
HiPerClockS
R1
R2
1k
1k
PCLK/nPCLK
Figure 4E. HiPerClockS PCLK/nPCLK Input
Driven by an SSTL Driver (delete this figure
Figure 4F. HiPerClockS PCLK/nPCLK Input Driven by
a 3.3V LVDS Driver
IDT⢠/ ICS⢠3.3V LVPECL FANOUT BUFFER
11
ICS8534AY-01 REV. A DECEMBER 6, 2007
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