ICS8534-01 Datasheet, PDF (10/20 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Differential Clock Input Interface
The CLK /nCLK accepts LVPECL, LVDS, LVHSTL and other
differential signals. Both V_SWING and V_OH must meet the V_PP and
V_CMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1
R2
50
50
3.3V
CLK
nCLK
HiPerClockS
3.3V
CML Built-In Pullup
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
100
nCLK
HiPerClockS
Figure 3A. HiPerClockS CLK/nCLK Input Driven by an
IDT Open Collector CML Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a Built-In Pullup CML Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
R4
125
125
3.3V
CLK
nCLK
HiPerClockS
R1
R2
84
84
3.3V
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
R5
100 - 200
R6
100 - 200
C1
C2
R1
R2
125 125
3.3V
CLK
nCLK
HiPerClockS
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
R4
120
120
3.3V
CLK
R1
R2
120
120
nCLK
HiPerClockS
Figure 3D. HiPerClockS CLK/nCLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
100
nCLK
HiPerClockS
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by an SSTL Driver
Figure 3F. HiPerClockS CLK/nCLK Input Driven by
a 3.3V LVDS Driver
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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ICS8534AY-01 REV. A DECEMBER 6, 2007