ICS854S057BI Datasheet, PDF (10/15 Pages) Integrated Device Technology – One LVDS output pair

ICS854S057BI Data Sheet
4:1, OR 2:1 LVDS CLOCK MULTIPLEXER W/INTERNAL INPUT TERMINATION
LVDS Driver Termination
A general LVDS interface is shown in Figure 3. Standard termination
for LVDS type output structure requires both a 100Ω parallel resistor
at the receiver and a 100Ω differential transmission line environment.
In order to avoid any transmission line reflection issues, the 100Ω
resistor must be placed as close to the receiver as possible. IDT
offers a full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 3 can be used with either
type of output structure. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these
outputs are LVDS compatible, the input receivers amplitude and
common mode input range should be verified for compatibility with
the output.
LVDS Driver
100Ω
+
LVDS
Receiver
–
100Ω Differential Transmission Line
Figure 3. Typical LVDS Driver Termination
Schematic Example
Figure 4 shows a schematic example of the ICS854S057BI. In this
example, the PCLK0/nPCLK0 and PCLK1/nPCLK1 inputs are used.
The decoupling capacitors should be physically located near the
power pin.
VDD
LVDS
Zo = 50
Zo = 50
VDD
Zo = 50
LVPECL Zo = 50
VDD
R1
1K
R1
1K
VDD
VDD
U1
ICS854057
VDD
R1
R3
680
680
1
2
3
4
VDD
PCLK0
VT0
5 ^nPCLK0
6
7
8
9
SEL1
SEL0
PCLK1
VT1
10
nPCLK1
GND
VDD
PCLK3
VT3
20
19
18
17
nPCLK3 ₁₆
Q
nQ
PCLK2
VT2
15
14
13
12
nPCLK2
GND
11
R2
R4
680
680
R6
18
(U1,1)
VDD (U1,20)
C1
0.1u
C2
0.1u
VDD=2.5V
Zo = 50
R5
100
Zo = 50
+
-
LVDS
Figure 4. ICS854S057BI LVDS Schematic Example
ICS854S057BGI REVISION A MARCH 29, 2010
10
©2010 Integrated Device Technology, Inc.