ICS8533I-01 Datasheet, PDF (10/17 Pages) Integrated Device Technology – DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 3.3V operating supply

ICS8533I-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V_SWING and V_OH must meet the V_PP
and V_CMR input requirements. Figures 4A to 4F show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
CML
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R1
R2
50
50
3.3V
PCLK
nPCLK _HiPerClockS
PCLK/nPCLK
3.3V
Zo = 50 Ohm
3.3V
R1
PCLK
100
nPCLK
Zo = 50 Ohm
HiPerClockS
CML Built-In Pullup
PCLK/nPCLK
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3. 3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3. 3V
R3
R4
125
125
3.3V
PCLK
nPCLK _HiPerClockS
I nput
R1
R2
84
84
3.3V
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
R5
100 - 200
R6
100 - 200
3.3V
R3
R4
84
84
C1
C2
R1
R2
125
125
3.3V
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
HiPerClockS
PCLK/nPCLK
3.3V
LVDS
Zo = 50 Ohm
R5
100
Zo = 50 Ohm
3.3V
3.3V
R3
R4
1K
1K
C1
PCLK
C2
nPC LK
HiPerClockS
PCLK/nPCLK
R1
R2
1K
1K
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 4F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
8533AGI-01
10
REV. A DECEMBER 6, 2007