ICS8533I-01 Datasheet, PDF (1/17 Pages) Integrated Device Technology – DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 3.3V operating supply

ICS8533I-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
F ^{The ICS8533I-01 is a low skew, high perfor-}
mance 1-to-4 Differential-to-3.3V LVPECL
EATURES
HiPerClockS™ _{Fanout Buffer and a member of the HiPerClockS™ • Four differential 3.3V LVPECL outputs}
family of High Performance Clock Solutions from
IDT. The ICS8533I-01 has two selectable clock ^{• Selectable differential CLK, nCLK or LVPECL clock inputs}
inputs. The CLK, nCLK pair can accept most standard dif-
ferential input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels. The clock enable is
internally synchronized to eliminate runt pulses on the out-
puts during asynchronous assertion/deassertion of the clock
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
enable pin.
• Maximum output frequency: 650MHz
Guaranteed output and part-to-part skew characteristics
make the ICS8533I-01 ideal for those applications demand-
ing well defined performance and repeatability.
• Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.5ns (maximum), CLK/nCLK
• Additive phase jitter, RMS: 0.060ps (typical)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
CLK_EN
CLK
nCLK
0
PCLK
nPCLK
1
CLK_SEL
D
Q
LE
PIN ASSIGNMENT
VEE 1
20 Q0
CLK_EN ^{2 19} nQ0
CLK_SEL 3
18 _VCC
CLK 4 17 Q1
Q0
nCLK 5 16 nQ1
nQ0
PCLK 6 15 Q2
nPCLK 7 14 nQ2
Q1
nc ⁸
13 _VCC
nQ1
nc 9 ¹² Q3
Q2
VCC 10 11 nQ3
nQ2
ICS8533I-01
Q3
20-Lead TSSOP
nQ3
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
8533AGI-01
1
REV. A DECEMBER 6, 2007