ICS813252I-02 Datasheet, PDF (10/22 Pages) Integrated Device Technology – VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER

ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS813252I-02
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V_CC, V_CCX, V_CCA, and
V should be individually connected to the power supply
CCO
plane through vias, and 0.01µF bypass capacitors should be used
for each pin. Figure 1 illustrates this for a generic V_CC pin and
also shows that V_CCA requires that an additional 10Ω resistor
along with a 10µF bypass capacitor be connected to the V_CCA pin.
V_DD
V_DDX
3.3V
.01µF
10Ω
10Ω
.01µF 10µF
V_DDA
.01µF 10µF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V /2 is
CC
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
CC
and R2/R1 = 0.609.
VCC
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLKx
nCLKx
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
IDT^™ / ICS^™ VCXO JITTER ATTENUATOR/MULTIPLIER
10
CS813252CKI-02 REV. A OCTOBER 22, 2008