ICS8536-02 Datasheet, PDF (1/17 Pages) Integrated Device Technology – Low Skew, 1-to-6, Dual Crystal/LVCMOS-to-3.3V, 2.5V LVPECL Fanout Buffer

Low Skew, 1-to-6, Dual Crystal/LVCMOS-to-
3.3V, 2.5V LVPECL Fanout Buffer
ICS8536-02
DATA SHEET
General Description
The ICS8536-02 is a low skew, high performance 1-to-6, Dual
Crystal or LVCMOS Input-to-3.3V, 2.5V LVPECL Fanout Buffer. The
ICS8536-02 has selectable crystal or single ended clock input. The
single ended clock input accepts LVCMOS or LVTTL input levels and
translates them to LVPECL levels. The output enable is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8536-02 ideal for those applications demanding well defined
performance and repeatability.
Features
• Six 3.3V, 2.5V differential LVPECL output pairs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Maximum output frequency: 266MHz
• Crystal frequency range: 14MHz – 40MHz
• Output skew: 55ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 1.85ns (maximum), 3.3V
• Additive phase jitter, RMS: 0.149ps (typical)
• Full 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
CLK_EN ^Pullup
CLK_SEL0 ^Pulldown
CLK_SEL1 ^Pulldown
XTAL_IN0
XTAL_OUT0
OSC
00
XTAL_IN1
XTAL_OUT1
OSC
01
CLK0 ^Pulldown
1X
D
Q
LE
Q0
nQ0
6 LVPECL Outputs
Q5
nQ5
Pin Assignment
nQ2 1
Q2 2
V_CC 3
nQ1 4
Q1 5
V_EE 6
nQ0 7
Q0 8
CLK_SEL0 9
XTAL_IN0 10
XTAL_OUT0 11
CLK_EN 12
24 Q3
23 nQ3
22 VCC
21 Q4
20 nQ4
19 VCC
18 Q5
17 nQ5
16 CLK_SEL1
15 XTAL_OUT1
14 XTAL_IN1
13 CLK0
ICS8536-02
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
ICS8536AG-02 REVISION A JULY 21, 2010
1
©2010 Integrated Device Technology, Inc.