5T915 Datasheet, PDF (1/21 Pages) Integrated Device Technology – 2.5V Differential 1:5 Clock Buffer Terabuffer

2.5V Differential 1:5 Clock Buffer
Terabuffer™
5T915
DATA SHEET
FEATURES:
• Guaranteed Low Skew < 60ps (max)
• Very low duty cycle distortion < 300ps (max)
• High speed propagation delay < 2ns (max)
• Up to 250MHz operation
• Very low CMOS power levels
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input
interface
• Selectable differential or single-ended inputs and five differential
outputs
• 2.5V VDD
• Available in TSSOP package
DESCRIPTION:
The 5T915 2.5V differential (DDR) clock buffer is a user-selectable sin-
gle-ended or differential input to five differential outputs built on advanced
metal CMOS technology. The differential clock buffer fanout from a single
or differential input to five differential or single-ended outputs reduces
loading on the preceding driver and provides an efficient clock distribution
network. The 5T915 can act as a translator from a differential HSTL,
eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL
input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is
controlled by 3-level input signals that may be hard-wired to appropriate
high-mid-low levels.
The 5T915 true or complementary outputs can be asynchronously
enabled/disabled. Multiple power and grounds reduce noise.
APPLICATIONS:
• Clock and signal distribution
FUNCTIONAL BLOCK DIAGRAM
5T915 REVISION A 11/3/15
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