ICS952801 Datasheet, PDF (9/22 Pages) Integrated Circuit Systems – Programmable Timing Control HubTM for K8TM processor

Integrated
Circuit
Systems, Inc.
I²C Table: Function Control Register
Byte 0
Pin #
Name
Bit 7
-
Bit 6
26
Bit 5
-
Bit 4
25
Bit 3
-
Bit 2
-
Bit 1
-
PDEN
PCICLK7
WDS_EN
PCICLK6
AFS1
AFS0
AEN1
Bit 0
-
AEN0
ICS952801
Advance Information
Control
Function
PD# Enable
Output Control
WD Soft Enable
Output Control
Async Rom SEL_1
Async Rom SEL_0
Zclk/Agp/Pci Freq
Source Select Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
See Table 3: Async Z-CLK
Frequency Selection Table
See Table 4 : ZCLK, AGP &
PCI Frequency Source
Decode Table
PWD
1
1
1
1
0
0
0
0
Table 3: Asynchronous ZCLK Frequency Selection Table
Byte0 Bit3 Byte0 Bit2
ZCLK Frequency
0
0
64.01
0
1
72.01
1
0
82.30
1
1
144.02
Table 4: ZCLK, AGP & PCI Frequency Source Decode Table
Byte0 Bit1
Byte0 Bit0
ZCLK & AGP & PCI
0
0
See Table 1, QuadRom
Frequency Table
0
1
N-Programming for
AGP/PCI/ZCLK
1
0
See Table 1 for AGP/PCI,
Table 3 for ZCLK
1
1
N-Programming for AGP/PCI,
Table 3 for ZCLK
I²C Table: Async N-Programming Frequency Select Register
Byte 1
Pin #
Name
Control
Function
Type
0
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
N PLL3 Div7
RW
-
N PLL3 Div6
The decimal
RW
-
N PLL3 Div5
representation of N
RW
-
N PLL3 Div4
PLL2 Div (7:0) + 8 is
equal to VCO divider
RW
-
N PLL3 Div3
value for PLL2. Default
RW
-
N PLL3 Div2
at power up =
RW
-
N PLL3 Div1
66.67MHz
RW
-
N PLL3 Div0
RW
-
I²C Table: Reserved Register
Byte 2
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
1
PWD
-
0
-
1
-
0
-
0
-
0
-
1
-
1
-
1
1
PWD
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
0719—01/22/03
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