ICS952801 Datasheet, PDF (13/22 Pages) Integrated Circuit Systems – Programmable Timing Control HubTM for K8TM processor

Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
I²C Table: Output Divider Control Register
Byte 15
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
Reserved
Reserved
CPU Div3
CPU Div2
CPU Div1
CPU Div0
Control
Function
Reserved
Reserved
Reserved
Reserved
CPU divider ratio can
be configured via these
4 bits individually.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
-
-
-
-
-
-
-
-
See Table 5: Divider Ratio
Combination Table
PWD
X
X
X
X
X
X
X
X
Table 5: CPU Divider Ratio Combination Table
Bit
00
01
1
00
0000
2
0100
Divider (3:2)
2
4
10
1000
01
0001
3
0101
6
1001
10
0010
5
0110
10
1010
11
0011
7
0111
14
1011
LSB
Address
Div
Address
Div
Address
I²C Table: Output Divider Control Register
Byte 16
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
11
MSB
4
8
8
1100
16
12
1101
24
20
1110
40
28
1111
56
Div
Address
Div
0
1
PWD
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
I²C Table: Output Divider Control Register
Byte 17
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
Reserved
CPUINV
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
CPU Phase Invert
Reserved
Reserved
Reserved
Reserved
0719—01/22/03
13
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
Default
-
-
-
-
1
-
-
-
Inverse
-
-
-
-
PWD
X
X
X
X
X
X
X
X