ICS952801 Datasheet, PDF (2/22 Pages) Integrated Circuit Systems – Programmable Timing Control HubTM for K8TM processor

Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
General Description
The ICS952801 is a two chip clock solution for desktop designs using SIS 755/760 style chipsets. When used with a zero
delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks
signals for such a system.
The ICS952801 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I²C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
X1
XTAL
X2
PLL2
Frequency
Dividers
PD#
CPU_STOP#
PCI_STOP#
FS (4:0)
SEL24_48MHZ
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
48MHz
24_48MHz
REF (2:0)
CPUCLK8T (1:0)
CPUCLK8C (1:0)
AGPCLK (1:0)
PCICLK (5:0)
PCICLKF (1:0)
ZCLK (1:0)
Power Groups
Pin Number
VDD
GND
1
5
31
28
38
36
Description
REF Output, Crystal
24/48MHz, Fix Analog, Fix Digital
CPU PLL, CPU Analog, MCLK
0719—01/22/03
2