ICS950508 Datasheet, PDF (9/19 Pages) Integrated Circuit Systems – Programmable Timing Control HubTM for PII/IIITTM

Integrated
Circuit
Systems, Inc.
Byte 17: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PCI_INV
3V66_INV
SD_INV
CPU_INV
APIC Div 3
APIC Div 2
APIC Div 1
APIC Div 0
PWD
Description
X PCICLK Phase Inversion bit
X 3V66 Phase Inversion bit
X SDRAM Phase Inversion bit
X CPUCLK Phase Inversion bit
X IOAPIC clock divider ratio can be
X configured via these 4 bits individually. For
X divider selection table refer to table 2.
X Default at power up is latched FS divider.
Table 1
Table 2
Div (3:2)
00 01 10 11
Div (1:0)
00
/2 /4 /8 /16
01
/3 /6 /12 /24
10
/5 /10 /20 /40
11
/7 /14 /28 /56
Div (3:2)
00 01 10 11
Div (1:0)
00
/4 /8 /16 /32
01
/3 /6 /12 /24
10
/5 /10 /20 /40
11
/9 /18 /36 /72
Byte 18: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SD_Skew 0
SD_Skew 1
Reserved
Reserved
CPU_Skew 1
CPU_Skew 0
Reserved
Reserved
PWD
Description
1 ^{These 2 bits delay the SDRAM with respect to}
CPUCLK
0 _{00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps}
0 Reserved
0 Reserved
1 ^{These 2 bits delay the CPU clock with respect}
to all other clocks.
0 _{00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps}
0 Reserved
0 Reserved
Byte 19: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PCI_Skew 3
PCI_Skew 2
PCI_Skew 1
PCI_Skew 0
3V66_Skew 1
3V66_Skew 0
Reserved
Reserved
PWD
Description
0 These 4 bits can change the 3V66 to PCI
0
1
skew from 1.4ns - 2.9ns. Each binary
increment or decrement of PCI_SKEW (3:0)
will increase or decrease the delay of the PCI
0 clocks by 100ps.
1 ^{These 2 bits delay the 3V66 with respect to}
CPUCLK
0 _{00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps}
0 Reserved
0 Reserved
0470E—04/06/05
9
ICS950508