ICS950508 Datasheet, PDF (10/19 Pages) Integrated Circuit Systems – Programmable Timing Control HubTM for PII/IIITTM

Integrated
Circuit
Systems, Inc.
Byte 20: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
Reserved
APIC_Skew 3
APIC_Skew 2
APIC_Skew 1
APIC_Skew 0
PWD
Description
0 Reserved
0 Reserved
0 Reserved
0 Reserved
0 ^{These 4 bits can change the 3V66 to APIC}
skew from 1.4ns - 2.9ns. Default at power
0 _{up is - 2.5ns. Each binary increment or}
1 ^{decrement of APIC_SKEW (3:0) will}
increase or decrease the delay of the PCI
0 _{clocks by 100ps.}
Byte 21: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
24/48_Slew 1
24/48_Slew 0
3V66_Slew 1
3V66_Slew 0
APIC_Slew 1
APIC_Slew 0
REF_Slew 1
REF_Slew 0
PWD
Description
0 _{24/48 MHz clock slew rate control bits.}
1 ^{10 = strong: 11 = normal; 01 = weak}
0 _{3V66 clock slew rate control bits.}
1 ^{10 = strong: 11 = normal; 01 = weak}
0 _{IOAPIC clock slew rate control bits.}
1 ^{10 = strong: 11 = normal; 01 = weak}
0 _{REF clock slew rate control bits.}
1 ^{10 = strong: 11 = normal; 01 = weak}
Byte 22: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SD_F Slew 1
SD_F Slew 0
SD(11:8) Slew 1
SD(11:8) Slew 0
SD(7:4) Slew 1
SD(7:4) Slew 0
SD(3:0) Slew 1
SD(3:0) Slew 0
PWD
Description
0 _{SDRAM_F clock slew rate control bits.}
1 ^{10 = strong: 11 = normal; 01 = weak}
0 _{SDRAM (11:8) clock slew rate control bits.}
1 ^{10 = strong: 11 = normal; 01 = weak}
0 _{SDRAM (7:4) clock slew rate control bits.}
1 ^{10 = strong: 11 = normal; 01 = weak}
0 _{SDRAM (3:0) clock slew rate control bits.}
1 ^{10 = strong: 11 = normal; 01 = weak}
Byte 23: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PCI (7:4) Slew 1
PCI (7:4) Slew 0
PCI (3:0) Slew 1
PCI (3:0) Slew 0
CPU 1 Slew 1
CPU 1 Slew 0
CPU 0 Slew 1
CPU 0 Slew 0
PWD
Description
0 _{PCI (7:4) clock slew rate control bits.}
1 ^{10 = strong: 11 = normal; 01 = weak}
0 _{PCI (3:0) clock slew rate control bits.}
1 ^{10 = strong: 11 = normal; 01 = weak}
0 _{CPUCLK 1 clock slew rate control bits.}
1 ^{10 = strong: 11 = normal; 01 = weak}
0 _{CPUCLK 0 clock slew rate control bits.}
1 ^{10 = strong: 11 = normal; 01 = weak}
0470E—04/06/05
10
ICS950508