ICS9250-23 Datasheet, PDF (9/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-23
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Group Timing Relationship Table
Group
CPU 66MHz
Offset Tolerance
CPU to SDRAM 2.5ns 500ps
CPU to 3V66 7.5ns 500ps
SDRAM to 3V66 0.0ns 500ps
3V66 to PCI 1.5-3.5ns 500ps
USB & DOT Asynch N/A
CPU 100MHz
Offset Tolerance
5.0ns 500ps
5.0ns 500ps
0.0ns 500ps
1.5-3.5ns 500ps
Asynch N/A
CPU 133MHz
Offset Tolerance
0.0ns 500ps
0.0ns 500ps
0.0ns 500ps
1.5-3.5ns 500ps
Asynch N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70º C; Supply Voltage V_DD = 3.3 V +/-5%, V_DDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
V_IH
Input Low Voltage
V_IL
Input High Current
I_IH
V_IN = V_DD
Input Low Current
I_IL1
V_IN = 0 V; Inputs with no pull-up resistors
Input Low Current
I_IL2
V_IN = 0 V; Inputs with pull-up resistors
Operating
I_DD3.3V Cl = 0 pF; Select @ 66M
Supply Current
I_DDL2.5V Cl = 0 pF; Select @ 66M
Power Down Current I_DD3.3VPD Cl = 0 pF; With Input to Vdd or Gnd
Input frequency
Input Capacitance¹
F_i
V_DD = 3.3 V
C_IN
Logic Inputs
Transition Time¹
Settling Time¹
Clk Stabilization¹
C_INX
T_Trans
T_S
T_Stab
X1 & X2 pins
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From V_DD = 3.3 V to 1% target Freq.
Delay¹
T_PZH,TPZL output enable delay(all outputs)
T_PHZ,T_PLZ output disable delay(all outputs)
1_{Guaranteed by design, not 100% tested in production.}
2
V_SS-0.3
-5
-5
-200
27
1
1
V_DD+0.3
0.8
5
119 280
3
25
600
14.318
5
45
3
1
3
3
10
10
V
V
µ^A
µ^A
µ^A
mA
µ^A
MHz
pF
pF
ms
ms
ms
ns
ns
Third party brands and names are the property of their respective owners.
9