ICS9250-23 Datasheet, PDF (7/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-23
Byte 0: Functionality and frequency select register (Default=0)
(1 = enable, 0 = disable)
Bit
Bit
(2, 7:4)
Bit 3
Bit 1
Bit 0
Description
Bit (2,7:4)
CPUCLK
MHz
SDRAM
MHz
00000
69.00
103.50
0 0 0 0 1 70.00
105.00
000 10
71.00
106.50
0 0 0 1 1 66.90
100.35
0 0 10 0
72.00
108.00
0 0 1 0 1 75.00
112.50
00 110
76.60
114.90
0 0 1 1 1 85.00
127.50
0 1000
68.00
102.00
0 1 0 0 1 74.00
111.00
0 1 0 1 0 140.00
0 1 0 1 1 133.33
0 1 1 0 0 150.00
140.00
133.33
150.00
0 1 1 0 1 155.00
155.00
0 1 1 1 0 166.00
166.00
0 1 1 1 1 166.00
166.00
1 0 0 0 0 111.77
111.77
1 0 0 0 1 104.78
104.78
1 0 0 1 0 109.51
109.51
1 0 0 1 1 100.90
100.90
1 0 1 0 0 117.00
117.00
1 0 1 0 1 123.75
123.75
1 0 1 1 0 133.33
133.33
1 0 1 1 1 142.50
142.50
1 1 0 0 0 136.00
102.25
1 1 0 0 1 140.00
105.00
1 1 0 1 0 143.00
107.50
1 1 0 1 1 133.90
100.68
1 1 1 0 0 146.67
110.00
1 1 1 0 1 149.33
112.00
1 1 1 1 0 153.30
115.29
1 1 1 1 1 166.67
125.32
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,6:4
0- Normal
1- Spread spectrum enable ± 0.25% Center Spread
0- Running
1- Tristate all outputs
3V66
MHz
69.00
70.00
71.00
66.90
72.00
75.00
76.60
85.00
68.00
74.00
70.00
66.67
75.00
77.50
83.00
111.00
74.52
69.86
73.01
67.27
78.50
82.50
88.89
95.00
68.50
70.00
72.00
67.45
73.33
74.67
77.24
83.34
PCICLK
34.50
35.00
35.50
33.45
36.00
37.50
38.40
42.50
34.00
37.00
35.00
33.33
37.50
38.75
41.50
55.80
37.26
34.93
36.50
33.63
39.25
41.25
44.44
47.50
34.25
35.00
36.00
33.73
36.67
37.33
38.62
41.67
IOAPIC
MHz
17.25
17.50
17.75
16.73
18.00
18.75
19.20
21.25
17.00
18.50
17.50
16.67
18.75
19.38
22.75
27.90
18.63
17.46
18.25
16.82
19.63
20.62
22.22
23.75
17.13
17.50
18.00
16.86
18.33
18.67
19.30
20.83
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3.
PWD
00100
Note 1
0
1
0
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