English
Language : 

ICS9250-23 Datasheet, PDF (10/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™
ICS9250-23
Electrical Characteristics - CPUCLK
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless
PARAMETER
SYMBOL
CONDITIONS
TA = 0 - 70º C; VDD = 3.3
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Jitter, Cycle-to-Cycle
V
+/-5%,
VDDL
=
2.5
V
+/-5%;
CL
=
20 pF (unless otherwise
Output High Voltage
SYMBOL
CONDITOIOutNpSut Low Voltage
VOH4B IOH = -18 mA
VOL4B
IOH4B
IOL = 9 mA
VOH = 2.0 V
Output High Current
IOL4B
Tr4B
VOL@MIN = 1.0 V
Output Low Current
VOL@MAX =0.2V
VOL = 0.4 V, VOH = 2.0 V
Rise Time
Fall Time
Tf4B
VOH = 2.0 V, VOL = 0.4 V Duty Cycle
Dt4B
tjcyc-cyc4B1
VT = 1.25 V
VT = 1.25 V
Skew
Jitter, Cycle-to-Cycle
stated)
M2VV.I4NOOHL22BB
IOH2B
31IOL2B
0.4ttrf22BB11
T3701-24...5Y.2289.88515PVIIVVVVVOOOOOOHLOOLHLHHL==@=@=@M@1-MM-0M1123M2A2mAA..I1I4V2mN0XNXXA,=AV===V0,112.OUV.3.2HV3VNmmO7nVVV=LIAA5sT=V2S.00.4VV
0.4dt2B1 1.2VT = 11.2.65 V ns
45tsk2B1 49.6VT = 1.5255 V %
tjcyc-cyc2B1 432VT = 17.2550 V (CPpUs 133, SDRAM
100
1Guaranteed by design, not 100% tested in production.
Jitter, Cycle-to-Cycle
tjcyc-cyc1 VT = 1.25 V (all other select B)
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
10