ICS9161A Datasheet, PDF (9/15 Pages) Integrated Circuit Systems – Dual Programmable Graphics Frequency Generator

ICS9161A
Electrical Characteristics at 5.0V (continued)
AC Characteristics
DESCRIPTION
NAME
SYMBOL
MIN
TYP
MAX
UNITS
Reference oscillator value²
Reference
frequency
1/f
REF
Duty cycle for the input oscillator
defined as t₁/t_REF
Output oscillator values
Reference period
Input duty cycle
Output clock
periods
Duty cycle for the output oscillators³
Output duty cycle
Rise time for the output oscillators into a
25pF load
Rise times
f_REF
1
14.31818
60
MHz
t
16.6
69.8408
1000
ns
REF
t₁
25%
-
75%
-
t₂
8.33 (120
MHz)
-
2564 (390
kHz)
ns
t
45%
-
55%
-
3
t₄
-
-
3
ns
Fall time for the output oscillators into a
25pF load
Fall times
t₅
-
-
3
ns
Old frequency output
New frequency output
Time clock output remains high while
output muxes to reference frequency
freq1 output
freq2 output
f_REF mux time
t
-
-
-
-
freq1
t_freq2
-
-
-
-
t_A
0.5 t_REF
-
1.5t_REF
ns
Interval for serial programming and for
VCO changes to settle⁴
Time-out interval
t_time-out
2
5
10
ms
Time clock output remains high while
output muxes to new frequency value
t_freq2muxtime
t_B
0.5 t_REF
1.5 t_REF
-
ns
Time for the output oscillators to go into
tristate mode after OUTDIS-signal
Tristate
assertion
Time for the output oscillators to recover
from tristate mode after OUTDIS-signal CLK valid
goes high
Time for power-down mode of operation
to take effect
Power-down
t₆
-
25
-
ns
t₇
-
12
-
ns
t
-
25
-
ns
8
Time for recovery from power-down
mode to a valid CLK
Power-up
t₉
-
12
-
ns
Time for MCLK to go high after
PWRDWN is asserted high
MCLKOUT high
t₁₀
0
-
t_PWRDWN
ns
Delay of MCLK prior to f signal at
MCLK
output
MCLKOUT delay
t₁₁
0.5 t_MCLK
-
1.5 t_MCLK
ns
Clock period of serial clock
Set-up time
Hold time
Load command
t_serclk
2 • t_REF
-
t_SU
20
-
t
10
-
HD
t_ldcmd
0
-
2
ms
-
ns
-
ns
t₁+30
ns
Notes:
1. Parameter guaranteed by design and characterization. Not 100% tested in production.
2. For reference frequencies other than 14.81818 MHz, the pre-loaded ROM frequencies will shift proportionally.
3. Duty cycle is measured at CMOS threshold levels. At 5 volts, V_TH=2.5 volts.
4. If the interval is too short, see the time-out interval section in the control register definition.
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