ICS9161A Datasheet, PDF (4/15 Pages) Integrated Circuit Systems – Dual Programmable Graphics Frequency Generator

ICS9161A
Control Register Definitions
The control register allows the user to adjust various internal options. The register is defined as follows:
Bit
Bit Name
Default Value
Description
21
C5
20
C4
19
C3
18
C2
17
C1
16
C0
15
NS2
14
NS1
13
NS0
This bit determines which power-down mode the PD# pin will implement.
0
Power-down mode 1, C5=0, forces the MCLK signals to be a function of the
power-down register. Power-down mode 2, C5=1, turns off the crystal and
disables all outputs.
This bit determines which clock is multiplexed to VCLK during frequency
0
changes. C4=0 multiplexes the reference frequency to the VCLK output. C4=1
multiplexes MCLK to the VCLK output for applications where the graphics
controller cannot run as slow as f_REF.
This bit determines the length of the time-out interval. The time-out interval is
0
derived from the MCLK VCO. If this VCO is programmed to certain extremes,
the time-out interval may be too short. C3=0, normal time-out. C3=1, doubled
time-out interval.
0
Reserved, must be set to 0.
This bit adjusts the duty cycle. C1=0 causes a 1ns decrease in output high time.
1
C1=1 causes no adjustment. If the load capacitance is high, the adjustment can
bring the duty cycle closer to 50%.
0
Reserved, must be set to 0.
0
Acts on register 2. NS2=0 prescales the N counter by 2. NS2=1 prescales the P
counter value to 4.
0
Acts on register 1. NS1=0 prescales the N counter by 2. NS1=1 prescales the P
counter value to 4.
0
Acts on register 0. NS1=0 prescales the N counter by 2. NS0=1 prescales the P
counter value to 4.
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