ICS9161A Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – Dual Programmable Graphics Frequency Generator

Pin Configuration
ICS9161A
16-Pin 300- mil SOIC or PDIP
Pin Descriptions
PIN NUMBER PIN NAME
1
SEL0-CLK
2
SEL1-DATA
3
AVDD
4
OE
5
GND
6
X1
7
X2
8
MCLK
9
VCLK
10
ERROUT#
11
EXTCLK
12
INIT0
13
VDD
14
INIT1
15
EXTSEL
16
PD#
TYPE
IN
IN
PWR
IN
PWR
IN
OUT
OUT
OUT
OUT
IN
IN
PWR
IN
IN
IN
DESCRIPTION
Clock input in serial programming mode. Clock select pin in operating mode.
Has internal pull-down to GND.
Data input in serial programming mode. Clock select pin in operating mode. Has
internal pull-down to GND.
Power.
Tristates outputs when low. Has internal pull-up to VDD.
Ground.
Crystal input. This input includes XTAL load capacitance and feedback bias for
the crystal.
Crystal output which includes internal XTAL load capacitance.
Memory clock output.
Video clock output.
Output low signals an error in the serially programmed word.
External clock input. Has internal pull-up to VDD.
Selects initial power-up conditions, LSB. Has internal pull-down to GND.
Power.
Selects initial power-up conditions, MSB. Has internal pull-down to GND.
Selects external clock input (EXTCLK) as VCLK output. Has internal pull-up to
VDD.
Power-down pin, active low. Has internal pull-up to VDD.
2