ICS8523 Datasheet, PDF (9/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8523.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8523 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_DD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)_MAX = V_{DD_MAX} * I_{DD_MAX} = 3.465V * 50mA = 173.3mW
•
Power (outputs) = 32mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 4 * 32mW = 128mW
Total Power_{_MAX} (3.465V, with all outputs switching) = 173.3mW + 128mW = 301.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used . Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.301W * 66.6°C/W = 90.05°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance q_JA for 20-pin TSSOP, Forced Convection
q_JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8523BG
www.icst.com/products/hiperclocks.html
9
REV. B JULY 31, 2001