ICS8523 Datasheet, PDF (1/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8523 is a low skew, high perfor-
,&6
mance 1-to-4 Differential-to-LVHSTL fanout buffer
HiPerClockS™ _{and a member of the HiPerClockS™ family of High}
Performance Clock Solutions from ICS. The
ICS8523 has two selectable clock inputs. The
CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTL input levels. The clock enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8523 ideal for those applications demanding
well defined performance and repeatability.
FEATURES
• 4 differential 1.8V LVHSTL outputs
• Selectable CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 650MHz
• Translates any single-ended input signal to 1.8V LVHSTL
levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.6ns (maximum)
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK_EN
CLK
nCLK
0
PCLK
nPCLK
1
CLK_SEL
D
Q
LE
PIN ASSIGNMENT
GND 1 ²⁰ Q0
CLK_EN ^{2 19} nQ0
CLK_SEL 3
1 8 _VDDO
CLK 4 17 Q1
Q0
nCLK 5 16 nQ1
nQ0
PCLK 6 15 Q2
nPCLK 7 14 nQ2
Q1
nc ⁸
1 3 _VDDO
nQ1
nc 9 ¹² Q3
Q2
VDD 10 11 nQ3
nQ2
ICS8523
Q3
20-Lead TSSOP
nQ3
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
8523BG
www.icst.com/products/hiperclocks.html
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REV. B JULY 31, 2001