ICS844101I-312 Datasheet, PDF (9/13 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844101I-312
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844101I-312 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. V_DD, V_DDA, and
V_DDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each V_DDA. The 10Ω resis-
tor can also be replaced by a ferrite bead.
3.3V
V_DD
.01μF 10Ω
V_DDA
.01μF
10μF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844101I-312 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 3 below were determined using a 25MHz, 18pF
parallel resonant crystal and were chosen to minimize the
ppm error.
X1
18pF Parallel Crystal
XTAL_OUT
C1
27p
XTAL_IN
C2
27p
Figure 3. CRYSTAL INPUt INTERFACE
844101AGI-312
www.icst.com/products/hiperclocks.html
9
REV. A NOVEMBER 28, 2005