ICS844101I-312 Datasheet, PDF (4/13 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844101I-312
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 4A. OE CONTROL INPUT FUNCTION TABLE
Input
OE
0
1
Outputs
Q, nQ
HiZ
Enabled
TABLE 4B. SEL CONTROL INPUT FUNCTION TABLE
Input
SEL
Selected Source
0
XTAL_IN, XTAL_OUT
1
CLK
TABLE 4C. MODE CONTROL INPUT FUNCTION TABLE
Input
Mode
0
1
Condition
Q, nQ
Default Mode
Frequency Margining Mode
TABLE 4D. SERIAL MODE FUNCTION TABLE
Inputs
S_LOAD S_CLOCK
L
X
S_DATA
X
H
↑
Data
↓
L
X
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
Conditions
Serial inputs are ignored.
Serial input mode.
Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are latched.
844101AGI-312
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 28, 2005