ICS8432I-51 Datasheet, PDF (9/16 Pages) Integrated Circuit Systems – 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8432I-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS8432I-51 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 3 below
were determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error. The optimum C1 and C2
values can be slightly adjusted for different board layouts.
X1
18pF Parallel Cry stal
XTAL2
C1
22p
XTAL1
C2
22p
Figure 3. CRYSTAL INPUt INTERFACE
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUTx and nFOUTx are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
F_OUT
Z_o = 50Ω
Z_o = 50Ω
50Ω
1
RTT =
Z_o
(V + V / V –2) –2
OH
OL CC
F_IN
50Ω
RTT
V_CC - 2V
F_OUT
5
2 ^Zo
Z_o = 50Ω
3.3V
5
2 ^Zo
F
IN
Z
o
=
50Ω
3
2 ^Zo
3
2 ^Zo
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
8432BYI-51
www.icst.com/products/hiperclocks.html
9
REV. A MAY 28, 2003