ICS8432I-51 Datasheet, PDF (3/16 Pages) Integrated Circuit Systems – 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8432I-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
2, 3, 4,
28, 29,
30, 31, 32
5, 6
7
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
nc
Input
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition
Pulldown ^{of nP_LOAD input. LVCMOS / LVTTL interface levels.}
Input
Pulldown
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
Unused
No connect.
8, 16
9
10
11, 12
V_EE
TEST
Power
Output
V_CC
FOUT1, nFOUT1
Power
Output
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation. Output
driven LOW in parallel mode. LVCMOS / LVTTL interface levels.
Core supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
13
14, 15
17
18
19
20
21
22
23
V_CCO
FOUT0, nFOUT0
MR
S_CLOCK
S_DATA
S_LOAD
V_CCA
XTAL_SEL
TEST_CLK
Power
Output
Input
Input
Input
Input
Power
Input
Input
Output supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Pulldown
Pulldown
Pulldown
Pulldown
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the
inverted outputs nFOUTx to go high. When logic LOW, the internal
dividers and the outputs are enabled. Assertion of MR does not
effect loaded M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Pullup
Selects between crystal or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
24, 25
XTAL2, XTAL1
Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Parallel load input. Determines when data present at M8:M0 is
26
nP_LOAD
Input Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
8432BYI-51
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
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3
REV. A MAY 28, 2003