ICS8432I-51 Datasheet, PDF (6/16 Pages) Integrated Circuit Systems – 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8432I-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
V
Output High Voltage; NOTE 1
OH
V - 1.4
CCO
V - 1.0
CCO
V_OL
Output Low Voltage; NOTE 1
V_CCO - 2.0
V_CCO - 1.7
V_SWING Peak-to-Peak Output Voltage Swing
0.6
1.0
NOTE 1: Outputs terminated with 50 Ω to V_CCO - 2V. See "Parameter Measurement Information" section,
figure "3.3V Output Load Test Circuit".
Units
V
V
V
TABLE
5.
INPUT
FREQUENCY
CHARACTERISTICS,
V=
CC
V=
CCA
V
CCO
=
3.3V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
12
25
MHz
f_IN
Input Frequency XTAL1, XTAL2; NOTE 1
S_CLOCK
12
25
MHz
50
MHz
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 21 ≤ M ≤ 58. Using the
maximum frequency of 25MHz, valid values of M are 10 ≤ M ≤ 28.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum Typical Maximum
Fundamental
12
25
70
7
Units
MHz
Ω
pF
TABLE 7. AC CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
F_OUT
Output Frequency
31.25
700
tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 3
fVCO > 350MHz
25
tjit(per) Period Jitter, RMS; NOTE 1
3.5
tsk(o) Output Skew; NOTE 2, 3
15
t_R / t_F
Output Rise/Fall Time
20% to 80%
200
700
M, N to nP_LOAD
5
t_S
Setup Time S_DATA to S_CLOCK
5
S_CLOCK to S_LOAD
5
M, N to nP_LOAD
5
t_H
Hold Time S_DATA to S_CLOCK
5
S_CLOCK to S_LOAD
5
odc
Output Duty Cycle
N>1
48
52
t_PW
Output Pulse Width
N=1
t_PERIOD/2 - 150
t_PERIOD/2 + 150
t_LOCK
PLL Lock Time
1
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
%
ps
ms
8432BYI-51
www.icst.com/products/hiperclocks.html
REV. A MAY 28, 2003
6