ICS843034-01 Datasheet, PDF (9/22 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843034-01
FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
TABLE 4D. LVPECL DC CHARACTERISTICS, V_{CCO_A} = V_{CCO_B} = 2.375V TO 3.465V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
V_OH
Output High Voltage; NOTE 1
V_OL
Output Low Voltage; NOTE 1
V_SWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 Ω to V_{CCO_x} - 2V.
V_CCO - 1.4
V_CCO - 2.0
0.6
Maximum
V_CCO - 0.9
V_CCO - 1.7
1.0
Units
V
V
V
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, V_CC = V_CCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
XTAL_IN0, XTAL_OUT0
f_IN
Input
Frequency
XTAL_IN1, XTAL_OUT1
S_CLOCK
12
40
MHz
12
40
MHz
50
MHz
t_R / t_F
Rise Time S_CLOCK, S_DATA, S_LOAD
6
ns
NOTE: For the input crystal, CLK/nCLK and TEST_CLK frequency range, the M value must be set for the VCO to operate
within the 490MHz to 640MHz range. Using the minimum input frequency of 12MHz, valid values of M are 41 ≤ M ≤ 53.
with input divider P = ÷1 (P_DIV = 00). Using the maximum frequency of 40MHz, valid values of M are 13 ≤ M ≤ 16.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Test Conditions
Minimum Typical Maximum
Fundamental
12
40
50
7
1
Units
MHz
Ω
pF
mW
TABLE 7A. AC CHARACTERISTICS, V_CC = V_CCA = V_{CCO_A} = V_{CCO_B} = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_OUT
tjit(Ø)
tsk(o)
t_R / t_F
Output Frequency
Phase Jitter, RMS (Random);
NOTE 1
Output Skew; NOTE 2, 3
Output Rise/Fall Time
M, N to nP_LOAD
Integration Range:
637kHz - 5MHz
Measured @ the same
Output Frequency
20% to 80%
30.625
0.61
50
200
5
640
MHz
ps
ps
700
ps
ns
t
Setup Time S_DATA to S_CLOCK
S
S_CLOCK to S_LOAD
5
ns
5
ns
M, N to nP_LOAD
5
ns
t_H
Hold Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
ns
odc
Output Duty Cycle
50
%
t_LOCK
PLL Lock Time
1
ms
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
9