ICS843034-01 Datasheet, PDF (6/22 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843034-01
FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
MR nP_LOAD M
H
X
X
Inputs
N S_LOAD
X
X
S_CLOCK
X
S_DATA
X
Conditions
Reset. Forces outputs LOW.
L
L
Data Data
X
L
↑
Data Data
L
L
H
XX
L
L
H
XX
↑
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
↑
Data
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
L
Data
Contents of the shift register are passed to the
M divider and N output divider.
L
H
XX
↓
L
Data M divider and N output divider values are latched.
L
H
XX
L
X
X Parallel or serial input do not affect shift registers.
L
H
XX
H
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
↑
Data S_DATA passed directly to M divider as it is clocked.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE P = ÷1 (P_DIV = FLOAT)
VCO Frequency
(MHz)
M Divide
32
M5
16
M4
8
M3
4
M2
2
M1
1
M0
500
20
0
1
0
1
0
0
•
•
•
•
•
•
•
•
550
22
0
1
0
1
1
0
•
•
•
•
•
•
•
•
625
25
0
1
1
0
0
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or
TEST_CLK input frequency of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
*NX2 *NX1 *NX0
N Divider Value
Output Frequency (MHz)
Minimum Maximum
0
0
0
1
490
640
0
0
1
2
245
320
0
1
0
3
163.33
213.33
0
1
1
4
122.5
160
1
0
0
5
98
128
1
0
1
6
81.67
106.67
1
1
0
8
61.25
80
1
1
1
16
30.625
40
*NOTE: X denotes Bank A or Bank B
843034AY-01
www.icst.com/products/hiperclocks.html
6
REV. C NOVEMBER 28, 2005