ICS2595 Datasheet, PDF (9/12 Pages) Integrated Circuit Systems – User-Programmable Dual High-Performance Clock Generator

ICS2595
Table 2: Readback Sequence
Nibb-
le
FS0
FS1
FS2
FS3
1X
X
0
0
2X
X
1
0
3X
X
START bit (must be "0")
0
4X
X
"
1
5X
X
R/W* control bit (must be
"0")
0
6X
X
"
1
7X
X
LO (location LSB)
0
8X
X
"
1
9X
X
L1
0
10 X
X
"
1
11 X
X
L2
0
12 X
X
"
1
13 X
X
L3
0
14 X
X
"
1
15 X
X
L4 (location MSB)
0
16 X
X
"
1
17 X
X
X
0
18 X
X
X
1
19 X
X
X
0
20 X
X
X
1
21 X
X
X
0
22 X
X
X
1
23 X
X
X
0
24 X
X
X
1
25 X
X
X
0
26 X
X
X
1
27 X
X
X
0
28 X
X
X
1
29 X
X
X
0
30 X
X
X
1
31 X
X
X
0
32 X
X
X
1
33 X
X
X
0
34 X
X
X
1
35 X
X
X
0
36 X
X
X
1
37 X
X
X
0
38 X
X
X
1
39 X
X
STOP1 bit (must be "1")
0
40 X
X
"
1
41 X
X
STOP2 bit (must be '1")
0
42 X
X
"
1
FS0 becomes output after
write #42
43
X
X
0
Nibb-
le
FS0
FS1
FS2
FS3
44 "
X
X
1
45 N1 X
X
0
46 "
X
X
1
47 N2 X
X
0
48 "
X
X
1
49 N3 X
X
0
50 "
X
X
1
51 N4 X
X
0
52 "
X
X
1
53 N5 X
X
0
54 "
X
X
1
55 N6 X
X
0
56 "
X
X
1
57 N7 X
X
0
58 "
X
X
1
59
EXT-
FRE
X
X
0
60 "
X
X
1
61 D0 X
X
0
62 "
X
X
1
63 D1 X
X
0
64 "
X
X
1
X
X
FS0 returns to input mode
after write #64
"X" = don't care
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