ICS2595 Datasheet, PDF(4/12 Page) Integrated Circuit Systems – User-Programmable Dual High-Performance Clock Generator

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ICS2595 Datasheet, PDF (4/12 Pages) Integrated Circuit Systems – User-Programmable Dual High-Performance Clock Generator

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ICS2595

LATCHED FS inputs, not the FS inputs themselves, that

are interpreted by the internal logic. Interface logic resides

between the FS input pins and the programming/frequency

select logic. The appropriate "data write" procedure must

be observed. See the section "Digital Interface" in this

supplement for more information.

These rules must be followed:

â¢ Calculate Tmax and Tmin in seconds (where R is the

modulus of the reference divider and Fref is the

reference frequency in Hz) by the following formulas:

Tmin =

6* R

Fref

Tmax

4096*

Fref

â¢ A programming sequence consists of 42 successive

data writes to the device as shown in table 1: no delay

greater than Tmax or less than Tmin may occur between

any two successive writes.

â¢ A readback sequence consists of 64 successive data

writes to the device as shown in table 2: no delay

greater than Tmax or less than Tmin may occur between

any two successive writes.

â¢ Programming or readback sequences must be preceded

by a "quiet" period of at least 2* Tmax with no data

writes to the device unless it was immediately preceded

by another legal programming (or readback) sequence

(nothing else in between)

â¢ To change the active VCLK frequency selection, simply

write that data to the device; the last data written to the

part will always become VCLK frequency select after

a delay of approximately 2* Tmax. The internal shift

The FS0 & FS1 inputs are not used for programming, so it

is possible to use a two-pin interface for programming and

frequency selection (any bank of four VCLK addresses).

The reference frequency source must be operational for

proper execution of the programming sequence. If the on-

chip crystal oscillator is, allow at least 4* Tmax after the

device has valid power before attempting to program it.

Data Description

Location Bits (l0-L4)

The first five bits after the start bit control the frequency

location to be re-programmed according to this table. The

rightmost bit (the LSB) of the five shown in each

selection of the table is the first one sent.

Table 3 - Location Bit Programming

L(4.0)

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

LOCATION

VCLK Address 0

VCLK Address 1

VCLK Address 2

VCLK Address 3

VCLK Address 4

VCLK Address 5

VCLK Address 6

VCLK Address 7

VCLK Address 8

VCLK Address 9

VCLK Address 10

VCLK Address 11

VCLK Address 12

VCLK Address 13

VCLK Address 14

VCLK Address 15

MCLK Address 0

MCLK Address 1

MCLK Address 2

MCLK Address 4

Feedback Set Bits (N0-N7)

These bits control the feedback divider setting for the

location specified. The modulus of the feedback divider

will be equal to the value of these bits + 257. The least

significant bit (N0) is sent first.

Post-Divider Set Bits (D0-D1)

These bits control the post-divider setting for the location

specified according to this table. The least significant bit

(D0) is sent first.

Table 4 - Post-Divider Programming

D(1-0)

POST-DIVIDER

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