ICS2595 Datasheet, PDF (3/12 Pages) Integrated Circuit Systems – User-Programmable Dual High-Performance Clock Generator

ICS2595
Digital Inputs
The FS0-FS3 pins and the STROBE pin are used to select
the desired operating frequency of the VCLK output from
the 16 pre-programmed/user-programmed selections in
the ICS2595. These pins are also used to load new frequency
data into the registers.
The standard interface for the ICS2595 matches the interface
of the industry standard ICS2494. That is, the FS0-FS3
inputs access the device internals transparently when the
STROBE pin is high.
The digital interface for the ICS2595 (i.e. the FS0-FS3
inputs) may be optionally configured for edge-triggered
or level-activated operation of the STROBE pin. Example
timing requirements for each of the four options are
shown in Figure 1.
The programming sequence has been designed in such a
way that STROBE pin need not be used (as in situations
where the device is connected to the frequency select port
of some VGA chips).
VCLK Output Frequency Selection
To change the VCLK output frequency, simply write the
appropriate data to the ICS2595 FS inputs. The synthesizer
will output the new frequency programmed into that location
after a brief delay (see time-out specifications).
Upon device power-up, the selected frequency will be the
frequency pre-programmed into address 0 until a device
write is performed.
MCLK Output Frequency Selection
The MS0-MS1 pins are used to directly select the desired
operating frequency of the MCLK output from the four
pre-programmed/user-programmed selections in the
ICS2595. These inputs are not latched, nor are they involved
with memory programming operations.
Programming Mode Selection
In order to ensure that reliable programming under all
circumstances, we require that two "nibble" writes be
added to the beginning of the programming sequence that
was previously specified. The new sequence is shown in
Table 1. Note that the FS3 data is "0" for these first two
writes.
Because the same pins are used for both VCLK frequency
selection and re-programming the device frequency table,
a specific procedure must be observed for selection between
these modes. Device programming is accomplished by
Table 1: Programming Sequence
Nibble FS0 FS1
FS2
FS3
1X
X
0
0
2X
X
1
0
3X
X
START bit (must be "0")
0
4X
X
"
1
5X
X
R/W* control bit (must be
"0")
0
6X
X
"
1
7X
X
LO (location LSB)
0
8X
X
"
1
9X
X
L1
0
10 X
X
"
1
11 X
X
L2
0
12 X
X
"
1
13 X
X
L3
0
14 X
X
"
1
15 X
X
L4 (location MSB)
0
16 X
X
"
1
17 X
X
N0 (feedback LSB
0
18 X
X
"
1
19 X
X
N1
0
20 X
X
"
1
21 X
X
N2
0
22 X
X
"
1
23 X
X
N3
0
24 X
X
"
1
25 X
X
N4
0
26 X
X
"
1
27 X
X
N5
0
28 X
X
"
1
29 X
X
N6
0
30 X
X
"
1
31 X
X
N7(feedback MSB)
0
32 X
X
"
1
33 X
X
EXTFREQ (select if "1")
0
34 X
X
"
1
35 X
X
D0 (post-divder MSB)
0
36 X
X
"
1
37 X
X
D1 (post-divder MSB)
0
38 X
X
"
1
39 X
X
STOP1 bit (must be "1")
0
40 X
X
"
1
41 X
X
STOP2 bit (must be '1")
0
42 X
X
"
1
executing a "programming sequence". The latched FS2
input functions as a data input, and the latched FS3 input
functions as a data clock when this mode is activated. As
the latched FS3 data transitions from 0 to 1, the latched
FS2 data is shifted into the register. Note that it is the
3