ICS1526 Datasheet, PDF (9/11 Pages) Integrated Circuit Systems – Video Clock Synthesizer

ICS1526 Preliminary Data Sheet
Section 5 AC/DC Operating Conditions
Table 5-4 AC Characteristics
Parameter
Symbol
Min.
Typical Max. Units
Notes
General
VCO Frequency
VCO Gain
f_VCO
40
400
MHz
K
165
MHz/V
AC Inputs
OSC Input Frequency
f_OSC
0.02
Analog Input (HSYNC/VSYNC)
100
MHz
HSYNC Input Frequency
VSYNC Input Frequency
Input High Voltage
Input Low Voltage
Input Hysteresis
f_HSYNC
f_VSYNC
V_IH
V_IL
8
30
1.7
VSS - 0.3
0.2
10,000
120
5.5
1.1
0.8
kHz
Hz
V
V
V Schmitt trigger active
SDA, SCL, OSC Digital Inputs
Input High Voltage
V_IH
Input Low Voltage
V_IL
I²CADDR Digital Input
2
VSS - 0.3
5.5
V
0.8
V
Input High Voltage
Input Low Voltage
SDA Digital Output
V_IH
2
V_IL
VSS - 0.3
VDD+0.3 V
0.8
V
SDA Output Low Voltage
V_OL
SDA Output High Voltage
V_OH
0.4
V
IOUT = 3 mA
6.0
V
Determined by
external Rset resistor
LVCMOS Outputs (CLK, HSYNC_out, VSYNC_out, LOCK)
Output Frequency
Duty Cycle
Jitter, STJ, RMS
Jitter, STJ, pk-pk
F_s
2.5
200
MHz
VDDD = 3.3 V
S_DC
45
50
55
%
2
STJ
0.027
ns
30 kHz input to 50
STJ
0.200
ns
MHz output
Jitter, Input-Output
IOJ
2.500
ns HSYNC in to CLK out
HSYNC to HSYNC_out
propagation delay (without
Schmitt trigger)
2
9
ns
1
HSYNC to HSYNC_out
propagation delay (with
Schmitt-trigger)
6
10
ns
1
CLK to HSYNC_out/
VSYNC_out skew
1.0
ns
Clock/ HSYNC_out/
T_CR
VSYNC_out
Transition Time - Rise
1.0
1.5
ns
2
MDS1526 I
9
Revision 020304
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