ICS1526 Datasheet, PDF (5/11 Pages) Integrated Circuit Systems – Video Clock Synthesizer

ICS1526 Preliminary Data Sheet
Section 3 Register map summary
Section 3 Register map summary
Word
Address
00h
Name
Input
Control
Access Bit Name
Reset
Bit # Value
Description
R/W
CPen
0
1 Charge Pump Enable
0=External Enable via VSYNC, 1=Always Enabled
VSYNC_Pol 1
0 VSYNC Polarity (Charge Pump Enable)
Requires 00h:0=0
0=Coast (charge pump disabled) while VSYNC low,
1=Coast (charge pump disabled) while VSYNC high
HSYNC_Pol 2
0 HSYNC Polarity
0=Rising Edge, 1=Falling Edge
Reserved
3
0 Reserved
Reserved
4
0 Part requires a 0 for correct operation
Reserved
5
0 Reserved
EnPLS
6
1 Enable PLL Lock Output
0=Disable, 1=Enable
Reserved
7
0 Reserved
01h
Loop
R/W
ICP0-2
0-2
Control^*
Reserved
3
VCOD0-1
4-5
Reserved
6-7
ICP (Charge Pump Current)
Bit 2,1,0 = {000 =1 µA, 001 = 2 µA, 010 = 4 µA... 110 = 64 µA, 111 =
128 µA}
Reserved
VCO Divider
Bit 5,4 = {00 = ÷2, 01=÷4, 10=÷8, 11=÷16}
Reserved
02h
FdBk Div R / W
FBD0-7
0-7
0^*
Feedback Divider LSBs (bits 0-7)
03h
FdBk Div R / W
FBD8-11
0-3
1^*
Reserved
4-7
Feedback Divider MSBs (bits 8-11)
Divider setting = 12-bit word + 8
Minimum 12 = 000000000100
Maximum 4103 =111111111111
Reserved
04h
Reserved
Reserved
0-7
0 Reserved
05h
Schmitt- R / W
Schmitt
0
1 Schmitt-trigger control
trigger^*
control
0=Schmitt-trigger, 1=No Schmitt-trigger
Metal_Rev 1-7
0 Metal Mask Revision Number
06h
Output R / W
Reserved
0
0 Reserved
Enables
OE
1
0 Output Enable for CLK, HSYNC_out, VSYNC_out
0=High Impedance (disabled), 1=Enabled
Reserved
2-7
0 Reserved
MDS1526 I
5
Revision 020304
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel [phone] www.icst.com