ICS952702 Datasheet, PDF (8/17 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for K7 System

Integrated
Circuit
Systems, Inc.
ICS952702
I²C Table: Slew Rate Control Register
Byte 6 Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
PCIStr1
PCIStr0
PCIStr1
PCIStr0
PCIStr1
PCIStr0
AGPStr1
AGPStr0
Control Function
Type
0
1
PCICLK_F(1:0) Strength ^RW
00=.63x; 01=.75x; 10=.88x; 11=1x
Control
RW
Strength
PCICLK(2:0) Strength ^RW
00=.63x; 01=.75x; 10=.88x; 11=1x
Control
RW
Strength
PCICLK(5:3) Strength ^RW
Control
RW
00=.63x; 01=.75x; 10=.88x; 11=1x
Strength
AGPCLK Strength
Control
RW _{00=.7x; 01=.8x; 10=.9x; 11=1x Strength}
RW
I²C Table: Reserved Register
Byte 7 Pin #
Name
Control Function
Type
0
1
Bit 7
-
Reserved
Reserved
R
-
-
Bit 6
-
Reserved
Reserved
R
-
-
Bit 5
-
Reserved
Reserved
R
-
-
Bit 4
-
Reserved
Reserved
R
-
-
Bit 3
-
Reserved
Reserved
R
-
-
Bit 2
-
Reserved
Reserved
R
-
-
Bit 1
-
Reserved
Reserved
R
-
-
Bit 0
-
Reserved
Reserved
R
-
-
I²C Table: Byte Count Register
Byte 8 Pin #
Name
Control Function
Type
0
1
Bit 7
-
BC7
RW
-
-
Bit 6
-
BC6
RW
-
-
Bit 5
-
BC5
Writing to this register will RW
-
-
Bit 4
-
BC4
configure how many
RW
-
-
Bit 3
-
BC3
bytes will be read back, _RW
-
-
Bit 2
-
BC2
default is 0F = 15 bytes. _RW
-
-
Bit 1
-
BC1
RW
-
-
Bit 0
-
BC0
RW
-
-
I²C Table: Watchdog Timer Control Register
Byte 9 Pin #
Name
Control Function
Bit 7
-
WDSA control
WD soft alarm control
Bit 6
-
WDHRB
WD Hard Alarm Status
Read back
Bit 5
-
WDSRB
WD Soft Alarm Status
Read back
Bit 4
-
GR_EN
Gear Shift Reset Enable
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WDTCtrl
WD2
WD1
WD0
Watch Dog Time base
control
WD Timer Bit2
WD Timer Bit1
WD Timer Bit0
Type
RW
R
R
RW
RW
RW
RW
RW
0
Disable
Normal
1
Enable
Alarm
Normal
Alarm
Disable
Enable
290ms base
1160ms base
These bits represent X*290ms (or
1.16S) the watchdog timer will wait
before it goes to alarm mode. Default is
7 X 290ms =2s.
PWD
1
1
1
1
1
1
1
1
PWD
1
1
1
1
1
1
1
1
PWD
0
0
0
0
1
1
1
1
PWD
0
X
X
0
0
1
1
1
0795D—05/06/05
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