ICS952702 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for K7 System

Integrated
Circuit
Systems, Inc.
ICS952702
General Description
The ICS952702 is a two chip clock solution for desktop designs using SIS 746 style chipsets. When used with a zero delay
buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals
for such a system.
The ICS952702 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I²C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
X1
XTAL
X2
CPU_STOP#
PCI_STOP#
SCLK
SEL24_48MHZ
SEL12_48
PD#
SDATA
FS (4:0)
Control
Logic
PLL2
Frequency
Dividers
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
12_48MHZ
24_48MHZ
REF (2:0)
CPUCLKODT (1:0)
CPUCLKODC0
RESET#
IOAPIC (1:0)
PCICLKF (1:0)
PCICLK (5:0)
ZCLK (1:0)
AGPCLK (1:0)
Power Groups
Pin Number
VDD
GND
1
5
11
8
28
25
13,19
18,24
29
32
48
45
38
41
36
37
Description
REF output, Xtal
Hyper ZCLK output
24/48MHz fixed, Fixed PLL (Fix1)
PCICLK output
AGP output
IOAPIC output
CPU_T/C output
CPU PLL, CPU MCLK
0795D—05/06/05
2