ICS952702 Datasheet, PDF (7/17 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for K7 System

Integrated
Circuit
Systems, Inc.
ICS952702
I²C Table: Async Frequency Selection & Output Skew Control Register
Byte 4 Pin #
Name
Control Function
Type
0
1
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
ASYNC2
ASYNC1
ASYNC0
Reserved
ZCLKSkw1
ZCLKSkw0
Fix PLL Async Freq
Programming bits
Reserved
RW
See Table 2: Async Frequency Selection
RW
Table
RW
RW
-
-
RW ^{00:0ps; 01:250ps; 10:500ps; 11:750ps}
CPU-ZCLK Skew Control
This byte will advance or delay the skew
RW
by 250ps per step
Bit 1
-
Bit 0
-
AGPSkw1
AGPSkw0
CPU-AGP Skew Control
RW ^{00:0ps; 01:250ps; 10:500ps; 11:750ps}
This byte will advance or delay the skew
RW
by 250ps per step
PWD
0
0
0
1
0
1
0
1
Table 2: Asynchronous Frequency Selection Table
B4 bit7
B4 bit6
B4 bit5
ZCLK
AGP
0
0
0
Main PLL Main PLL
0
0
1
132
66
0
1
0
132
75.4
0
1
1
132
88
1
0
0
Main PLL Main PLL
1
0
1
132
66
1
1
0
132
75.4
1
1
1
132
88
PCI
Main PLL
33
37.7
44
Main PLL
33
33
33
Table 3: AGP Divider Ratio Combination Table
Bit
0
0
0
1
1
10
10
11
11
LSB
Address
Divider (3:2)
*01
1
2
4
100
8
3
101
6
5
110
10
15
111
30
Div
Address
Div
10
1000
1001
1010
1011
Address
11 MSB
4
8
16
1100 32
12
1101 24
20
1110 40
60
1111 120
Div Address Div
I²C Table: Revision ID & Output Divider Control Register
Byte 5 Pin #
Name
Control Function
Type
0
1
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
REV_ID3
REV_ID2
REV_ID1
REV_ID0
AGPDiv3
AGPDiv2
AGPDiv1
AGPDiv0
R
-
-
Revision ID
R
-
-
R
-
-
R
-
-
RW
AGP divider ratio can be _{RW See Table 3: Divider Ratio Combination}
configured via these 4
bits individually.
RW
Table
RW
PWD
0
0
0
1
1
1
0
1
0795D—05/06/05
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