ICS950908 Datasheet, PDF (8/22 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for P4™

Integrated
Circuit
Systems, Inc.
ICS950908
Preliminary Product Preview
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
35
36
37
38
41
42
43
44
PWD
1
1
1
1
1
1
1
1
Description
SDRAM7/DDRC3 (Active/Inactive)
SDRAM6/DDRT3 (Active/Inactive)
SDRAM5/DDRC2 (Active/Inactive)
SDRAM4/DDRT2 (Active/Inactive)
SDRAM3/DDRC1 (Active/Inactive)
SDRAM2/DDRT1 (Active/Inactive)
SDRAM1/DDRC0 (Active/Inactive)
SDRAM0/DDRT0 (Active/Inactive)
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Revision ID Bit3
Revision ID Bit2
Revision ID Bit1
Revision ID Bit0
Vendor ID Bit3
Vendor ID Bit2
Vendor ID Bit1
Vendor ID Bit0
PWD
X
X
X
X
0
0
0
1
Description
Revision ID values will be based on individual device's revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 7: Revision ID and Device ID Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
PWD
0
0
0
1
0
1
1
1
Description
Device ID values will be based on individual device
"01h" in this case.
Byte 8: Byte Count Read Back Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
0
0
0
0
1
1
1
1
Description
Note: Writing to this register will configure byte count and how
many bytes will be read back, default is 0F_H = 15 bytes.
0653A—07/26/04
8