ICS950908 Datasheet, PDF (7/22 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for P4™

Integrated
Circuit
Systems, Inc.
ICS950908
Preliminary Product Preview
Byte 1: CPU Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
Bit7
29
1 SDRAM11/DDRC5 (Active/Inactive)
Bit6
10
1 PCICLK_F (Active/Inactive)
Bit5
30
1 SDRAM10/DDRT5 (Active/Inactive)
Bit4
31
1 SDRAM9/DDRC4 (Active/Inactive)
Bit3
49
1 CPUT0_CS Free running control; 1 = free running; 0 = not free running
Bit2
32
1 SDRAM8/DDRT4 (Active/Inactive)
Bit1 53, 52
1 CPUCLKT/C (Active/Inactive)
Bit0
48
1 CPUCLKT1_CS (Active/Inactive)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
Bit7
46
1 FB_OUT Free running control; 1 = free running; 0 = not free running
Bit6
18
1 PCICLK5 (Active/Inactive)
Bit5
17
1 PCICLK4 (Active/Inactive)
Bit4
15
1 PCICLK3 (Active/Inactive)
Bit3
14
1 PCICLK2 (Active/Inactive)
Bit2
12
1 PCICLK1 (Active/Inactive)
Bit1
11
1 PCICLK0 (Active/Inactive)
Bit0 53, 52
1 CPUCLKT/C Free running control; 1 = free running; 0 = not free running
Byte 3: Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
Bit7
46
1 FB_OUT (Active/Inactive)
Bit6
-
1 SEL 24_48, 0=24Mhz 1=48MHz
Bit5
-
1 SD/DDR free running control; 1 = free running; 0 not free running
Bit4
56
1 REF1 (Active/Inactive)
Bit3
48
1 CPUT1_CS free running control; 1 = free running; 0 not free running
Bit2
8
1 AGPCLK 2 (Active/Inactive)
Bit1
7
1 AGPCLK 1 (Active/Inactive)
Bit0
6
1 AGPCLK 0 (Active/Inactive)
Byte 4: Frequency Select Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
-
-
20
21
49
1
PWD
X
X
X
X
1
1
1
1
Latched FS3
Latched FS2
Latched FS1
Latched FS0
48MHz (Active/Inactive)
24_48MHz (Active/Inactive)
CPUT0_CS (Active/Inactive)
REF0 (Active/Inactive)
Description
0653A—07/26/04
7