ICS950908 Datasheet, PDF (4/22 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for P4™

Integrated
Circuit
Systems, Inc.
ICS950908
Preliminary Product Preview
Pin Description Continued
PIN PIN
# NAME
29 DDRC5/SDRAM11
30 DDRT5/SDRAM10
31 DDRC4/SDRAM9
32 DDRT4/SDRAM8
33 GND
34 VDD3.3_2.5
35 DDRC3/SDRAM7
36 DDRT3/SDRAM6
37 DDRC2/SDRAM5
38 DDRT2/SDRAM4
39 GND
40 VDD3.3_2.5
41 DDRC1/SDRAM3
42 DDRT1/SDRAM2
43 DDRC0/SDRAM1
44 DDRT0/SDRAM0
45 BUF_IN
46 FBOUT
47 GND
48 CPUT1_CS
49 CPUT0_CS
50 VDDCPU2.5
51 VDDCPU3.3
52 CPUCLKC/CPUCLKODC
53 CPUCLKT/CPUCLKODT
54 GND
55 VDDREF
56 Vtt_PWRGD#**/REF1
PIN
TYPE
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
OUT
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
I/O
DESCRIPTION
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Ground pin.
2.5V or 3.3V nominal power supply voltage.
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Ground pin.
2.5V or 3.3V nominal power supply voltage.
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Input Buffers for memory outputs.
Memory feed back output.
Ground pin.
True clock of differential pair 2.5V push-pull CPU outputs.
True clock of differential pair 2.5V push-pull CPU outputs.
Power pin for the CPUCLKs. 2.5V
Power pin for the CPUCLKs. 3.3V
"Complementary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias / "Complementary" clocks of
differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up /
2.5V CPU clock output.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias / "True" clocks of differential pair CPU
outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock
output.
Ground pin.
Ref, XTAL power supply, nominal 3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / 14.318 MHz
reference clock.
Mode Pin - Power Management Input Control
MODE, Pin 6
(Latched Input)
0
1
Pin 26
PD#
(Input)
RESET#
(Output)
Pin 18
CPU_STOP#
(Input)
PCICLK5
(Output)
Pin 8
PCI_STOP#
(Input)
AGP2
(Output)
0653A—07/26/04
4