ICS932S825 Datasheet, PDF (8/20 Pages) Integrated Circuit Systems – Low Power Clock Chip for Serverworks HT2400 Servers

ICS932S825
AC Electrical Characteristics - Low Power Differential PCIe Outputs
T_A = 0 - 70°C; V_DD = 3.3 V +/-5%; C_L =2pF, R_S=33.2Ω
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Rising Edge Slew Rate
t_SLR
Differential Measurement
0.5
2
V/ns 1,2
Falling Edge Slew Rate
Slew Rate Variation
Maximum Output
Voltage
t_FLR
t_SLVAR
V_HIGH
Differential Measurement
0.5
Single-ended Measurement
Includes overshoot
2
V/ns 1,2
20
%
1
1150 mV
1
Minimum Output Voltage V_LOW
Includes undershoot
-300
mV
1
Differential Voltage
Swing
V_SWING
Differential Measurement
400
mV
Crossing Point Voltage
V_XABS
Single-ended Measurement
300
550
mV
Crossing Point Variation V_XABSVAR
Single-ended Measurement
140
mV
Duty Cycle
D_CYC
Differential Measurement
45
PCIe Jitter - Cycle to
Cycle
PCIeJ_C2C
Differential Measurement
55
%
125
ps
PCIe[6:0] Skew
PCIe_SKEW
Notes on Electrical Characteristics:
Differential Measurement
250
ps
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Slew rate measured through Vswing centered around differential zero}
3 _{Vxabs is defined as the voltage where CLK = CLK#}
4 _{Only applies to the differential rising edge (CLK rising and CLK# falling)}
5 _{Defined as the total variation of all crossing voltages of CLK rising and CLK# falling.}
6 _{All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz}
1
1,3,4
1,3,5
1
1
1
PCIe Phase Jitter Impact
Parameter
Conditions
Min Typical Max Units Notes
Output phase jitter
impact – PCIe* Gen1
θ_PCIe1
(including PLL BW 1.5-22 MHz, z =
0.54, Td=10 ns, Ftrk=1.5 MHz )
0
108
ps 1,2,3,4
Output phase jitter
impact - PCIe Gen2
θ_PCIe2
(including PLL BW5-16 MHz,
8 – 16 MHz, z = 0.54, Td=10 ns)
0
ps
3.1
RMS ^1,2,3,4
NOTES:
1. Post processed evaluation through Intel supplied Matlab scripts.
2. PCIe* Gen2 filter characteristics are subject to f inal ratification by PC ISIG. Please check the PCI* SIG f or the latest specif ication.
3. These jitter numbers are def ined f or a BER of 1E-12. Measured numbers at a smaller sample size have to be extrapolated to this BER target.
4. Guaranteed by design and characterization, not 100% tested in production.
1276D—10/25/07
8