ICS932S825 Datasheet, PDF (7/20 Pages) Integrated Circuit Systems – Low Power Clock Chip for Serverworks HT2400 Servers

ICS932S825
Absolute Maximum Ratings
Parameter
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
Ambient Operating Temp
Symbol
VDDA
VDD
Ts
Tambient
Min
Max Units Notes
GND + 4.5V V
1
GND +4.5V V
1
-50
150
°C
0
70
°C
Input ESD protection human body model ESD prot 2000
V
1
1_{Operation at these extremes is neither implied nor guaranteed}
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
Conditions
MIN TYP MAX UNITS NOTES
Input High Voltage
V_IH
2
V_DD + 0.3 V
1
Input Low Voltage
V_IL
V_SS - 0.3
0.8
V
1
Input High Current
I_IH
V_IN = V_DD
-5
5
uA
1
Input Low Current
I_IL1
V_IN = 0 V; Inputs with no pull-up
-5
resistors
I_IL2
V_IN = 0 V; Inputs with pull-up
resistors
-200
uA
1
uA
1
Operating Current
Powerdown Current
Input Frequency³
Pin Inductance¹
I_DD3.3OP
I_DD3.3PD
F_i
L_pin
all outputs driven
all diff pairs Low/Low
V_DD = 3.3 V
250 mA
15
mA
14.318
MHz
3
7
nH
1
Input Capacitance¹
C_IN
C_OUT
Logic Inputs
Output pin capacitance
5
pF
1
6
pF
1
C_INX
X1 & X2 pins
5
pF
1
Clk Stabilization^1,2
T_STAB
From V_DD Power-Up or de-assertion
of PD# to 1st clock
3
ms
1,2
Modulation Frequency
Triangular Modulation
30
33
kHz
1
SMBus Voltage
V_DD
2.7
5.5
V
1
Low-level Output Voltage
Current sinking at
V_OL = 0.4 V
V_OL
I_PULLUP
@ I_PULLUP
0.4
V
1
4
mA
1
SCLK/SDATA
Clock/Data Rise Time³
T_RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000 ns
1
SCLK/SDATA
Clock/Data Fall Time³
T_FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3 _{Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet}
ppm frequency accuracy on PLL outputs.
1276D—10/25/07
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