ICS9148-11 Datasheet, PDF (8/14 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUMTM

ICS9148 - 11
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP#
is synchronized by theICS9148-11. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs.All other clocks
will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that
guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside
the ICS9148-11.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-11. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by theICS9148-11 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse)
is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed.
PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
(Drawing shown on next page.)
8